CP3BT23_14 Datasheet, PDF (230/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Master Transmit
After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a
byte, software must:
1. Check that the BER and NEGACK bits in the ACBST register are clear and the ACBST.SDAST bit is
set. Also, if the ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear.
2. Write the data byte to be transmitted to the ACBSDA register.
When the slave responds with a negative acknowledge, the ACBST.NEGACK bit is set and the
ACBST.SDAST bit remains cleared. In this case, if the ACBCTL1.INTEN bit is set, an interrupt is sent to
the core.
Master Receive
After becoming the bus master, the device can start receiving data on the ACCESS.bus. To receive a
byte, software must:
1. Check that the ACBST.SDAST bit is set and the ACBST.BER bit is clear. Also, if the
ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear.
2. Set the ACBCTL1.ACK bit, if the next byte is the last byte that should be read. This causes a negative
acknowledge to be sent.
3. Read the data byte from the ACBSDA register.
Master Stop
A Stop Condition may be issued only when this device is the active bus master (ACBST.MASTRER = 1).
To end a transaction, set the ACBCTL1.STOP bit before clearing the current stall bit (i.e., the
ACBST.SDAST, ACBST.NEGACK, or ACBST.STASTR bit). This causes the module to send a Stop
Condition immediately, and clear the ACBCTL1.STOP bit.
Master Bus Stall
The ACB module can stall the ACCESS.bus between transfers while waiting for the core’s response. The
ACCESS.bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is
interpreted as the beginning of the following bus operation. Software must make sure that the next
operation is prepared before the bit that causes the bus stall is cleared.
The bits that can cause a stall in master mode are:
• Negative acknowledge after sending a byte (ACBSTNEGACK = 1).
• ACBST.SDAST bit is set.
• If the ACBCTL1.STASTRE bit is set, after a successful start (ACBST.STASTR = 1).
Repeated Start
A repeated start is performed when this device is already the bus master (ACBST.MASTER = 1). In this
case, the ACCESS.bus is stalled and the ACB waits for the core handling due to: negative acknowledge
(ACBST.NEGACK = 1), empty buffer (ACBST.SDAST = 1), or a stop-after-start (ACBST.STASTR = 1).
For a repeated start:
1. Set the ACBCTL1.START bit.
2. In master receive mode, read the last data item from the ACBSDA register.
3. Follow the address send sequence, as described in “Sending the Address Byte”.
4. If the ACB was waiting for handling due to ACBST.STASTR = 1, clear it only after writing the
requested address and direction to the ACBSDA register.
230 ACCESS.bus Interface
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