CP3BT23_14 Datasheet, PDF (248/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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25.2.1 Mode 1: Processor-Independent PWM
Mode 1 is the Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a
specified width and duty cycle, and which also provides a separate general-purpose timer/counter.
Figure 25-4 is a block diagram of the Multi-Function Timer configured to operate in Mode 1. Timer/Counter
1 (TCNT1) functions as the time base for the PWM timer. It counts down at the clock rate selected for the
counter. When an underflow occurs, the timer register is reloaded alternately from the TCRA and TCRB
registers, and counting proceeds downward from the loaded value.
On the first underflow, the timer is loaded from the TCRA register, then from the TCRB register on the
next underflow, then from the TCRA register again on the next underflow, and so on. Every time the
counter is stopped and restarted, it always obtains its first reload value from the TCRA register. This is
true whether the timer is restarted upon reset, after entering Mode 1 from another mode, or after stopping
and restarting the clock with the Timer/Counter 1 clock selector.
The timer can be configured to toggle the TA output bit on each underflow. This generates a clock signal
on the TA output with the width and duty cycle determined by the values stored in the TCRA and TCRB
registers. This is a “processor-independent” PWM clock because once the timer is set up, no more action
is required from the CPU to generate a continuous PWM signal.
The timer can be configured to generate separate interrupts upon reload from the TCRA and TCRB
registers. The interrupts can be enabled or disabled under software control. The CPU can determine the
cause of each interrupt by looking at the TAPND and TBPND bits, which are updated by the hardware on
each occurrence of a timer reload.In Mode 1, Timer/Counter 2 (TCNT2) can be used either as a simple
system timer, an external event counter, or a pulseaccumulate counter. The clock counts down using the
clock selected with the Timer/Counter 2 clock selector. It generates an interrupt upon each underflow if the
interrupt is enabled with the TDIEN bit.
Timer 1
Clock
Reload A = Time 1
TCRA_n
Underflow
Timer/Counter 1
TCNT1_n
Underflow
Reload B = Time 2
TCRB_n
TAPND
TAIEN
TAEN
TBIEN
TBPND
Timer
Interrupt A
TAn
Timer
Interrupt B
Timer 2
Clock
Timer/Counter 2
TCNT2_n
TDIEN
TDPND
Timer
Interrupt D
Clock
Selector
TBn
DS451
Figure 25-4. Processor-Independent PWM Mode
248 Multi-Function Timer
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