CP3BT23_14 Datasheet, PDF (182/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Name
ATDR0
ATDR
ATDR2
ATDR3
AGCR
AISCR
ARSCR
ATSCR
ACCR
ADMACR
Table 19-1. Audio Interface Registers (continued)
Address
FF FD4Ch
FF FD4Eh
FF FD50h
FF FD52h
FF FD54h
FF FD56h
FF FD58h
FF FD5Ah
FF FD5Ch
FF FD5Eh
Description
Audio Transmit DMA Register 0
Audio Transmit DMA Register 1
Audio Transmit DMA Register 2
Audio Transmit DMA Register 3
Audio Global Configuration Register
Audio Interrupt Status and Control Register
Audio Receive Status and Control Register
Audio Transmit Status and Control Register
Audio Clock Control Register
Audio DMA Control Register
19.7.1 Audio Receive FIFO Register (ARFR)
The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive
FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift
Register (ARSR), when the ARSR is full.
In 8-bit mode, only the lower byte of the ARFR is used, and the upper byte contains undefined data. In 16-
bit mode, a 16-bit word is copied from ARSR into the receive FIFO. The CPU bus master has read-only
access to the receive FIFO, represented by the ARFR register. After reset, the receive FIFO (ARFR)
contains undefined data.
7
0
ARFL
15
ARFL
ARFH
8
ARFH
The Audio Receive FIFO Low Byte shows the lower byte of the receive FIFO location
currently addressed by the Receive FIFO Read Pointer (RRP).
The Audio Receive FIFO High Byte shows the upper byte of the receive FIFO location
currently addressed by the Receive FIFO Read Pointer (RRP). In 8-bit mode, ARFH contains
undefined data.
19.7.2 Audio Receive DMA Register n (ARDRn)
The ARDRn register contains the data received within slot n, assigned for DMA support. In 8-bit mode,
only the lower 8-bit portion of the ARDRn register is used, and the upper byte contains undefined data. In
16-bit mode, a 16-bit word is transferred from the Audio Receive Shift Register (ARSR) into the ARDRn
register. The CPU bus master, typically a DMA controller, has read-only access to the receive DMA
registers. After reset, these registers are clear.
7
0
ARDL
15
ARDL
ARDH
8
ARDH
The Audio Receive DMA Low Byte field receives the lower byte of the audio data copied
from the ARSR.
In 16-bit mode, the Audio Receive DMA High Byte field receives the upper byte of the audio
data word copied from ARSR. In 8-bit mode, the ARDH register holds undefined data.
182 Advanced Audio Interface
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