CP3BT23_14 Datasheet, PDF (28/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Name
BCFG
IOCFG
SZCFG0
SZCFG1
SZCFG2
Table 6-3. Bus Control Registers
Address
FF F900h
FF F902h
FF F904h
FF F906h
FF F908h
Description
BIU Confifguration Register
I/O Zone Configuration Register
Static Zone 0 Configuration Register
Static Zone 1 Configuration Register
Static Zone 2 Configuration Register
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6.4.1 BIU Configuration Register (BCFG)
The BCFG register is a byte-wide, read/write register that selects early-write or late-write bus cycles. At
reset, the register is initialized to 07h. The register format is shown below.
7
3
2
1
0
Reserved
1
1
EWR
EWR
The Early Write bit controls write cycle timing.
0 – Late-write operation (2 clock cycles to write).
1 – Early-write operation.
At reset, the BCFG register is initialized to 07h, which selects early-write operation. However, late-write
operation is required for normal device operation, so software must change the register value to 06h. Bits
1 and 2 of this register must always be set when writing to this register.
6.4.2 I/O Zone Configuration Register (IOCFG)
The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of
accesses to the 256-byte I/O Zone memory space (FF FB00h to FF FBFFh). The registers associated with
Port B and Port C reside in the I/O memory array. At reset, the register is initialized to 069Fh. The register
format is shown below.
7
6
5
BW
Reserved
4
3
HOLD
2
0
WAIT
15
10
9
8
Reserved
IPST
Res.
WAIT
HOLD
BW
IPST
The Memory Wait Cycles field specifies the number of TIW (internal wait state) clock cycles
added for each memory access, ranging from 000 binary for no additional TIW wait cycles to
111 binary for seven additional TIW wait cycles.
The Memory Hold Cycles field specifies the number of Thold clock cycles used for each
memory access, ranging from 00b for no T_hold cycles to 11b for three T_hold clock cycles.
The Bus Width bit defines the bus width of the IO Zone.
0 – 8-bit bus width.
1 – 16-bit bus width (default)
The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus
cycle accesses a different zone. No idle cycles are required for on-chip accesses.
0 – No idle cycle (recommended).
1 – Idle cycle.
28
Memory
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