CP3BT23_14 Datasheet, PDF (223/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
22.5.2 MICROWIRE Control Register (MWCTL1)
The MWCTL1 register is a word-wide, read/write register used to control the Microwire module. To avoid
clock glitches, the MWEN bit must be clear while changing the states of any other bits in the register. At
reset, all non-reserved bits are cleared. The register format is shown below.
7
6
5
4
3
2
1
0
SCM
EIW
EIR
EIO
ECHO
MOD
MNS
MWEN
15
MWEN
SCDV
9
0
SCIDL
The Microwire Enable bit controls whether the Microwire interface module is enabled.
0 – Microwire module disabled.
1 – Microwire module enabled.
Clearing this bit disables the module, clears the status bits in the Microwire status register
(the BSY, RBF, and OVR bits in MWSTAT), and places the Microwire interface pins in the
states described below.
Pin
MSK
MWCS
MDIDO
MDODI
Table 22-3.
State When Disabled
Master – SCIDL Bit Slave – Input
Input
Master – Input Slave – TRI-STATE
Master – Known value Slave – Input
MNS
MOD
ECHO
EIO
The Master/Slave Select bit controls whether the CP3BT23 is a master or slave. When clear,
the device operates as a slave. When set, the device operates as the master.
0 – CP3BT23 is slave.
1 – CP3BT23 is master.
The Mode Select bit controls whether 8or 16bit mode is used. When clear, the device
operates in 8-bit mode. When set, the device operates in 16-bit mode. This bit must only be
changed when the module is disabled or idle (MWSTAT.BSY = 0).
0 – 8-bit mode.
1 – 16-bit mode.
The Echo Back bit controls whether the echo back function is enabled in slave mode. This bit
must be written only when the Microwire interface is idle (MWSTAT.BSY=0). The ECHO bit is
ignored in master mode. The MWDAT register is valid from the time the register has been
written until the end of the transfer. In the echo back mode, MDODI is transmitted (echoed
back) on MDIDO if the MWDAT register does not contain any valid data. With the echo back
function disabled, the data held in the MWDAT register is transmitted on MDIDO, whether or
not the data is valid.
0 – Echo back disabled.
1 – Echo back enabled.
The Enable Interrupt on Overrun bit enables or disables the overrun error interrupt. When
set, an interrupt is generated when the Receive Overrun Error bit (MWSTAT.OVR) is set.
Otherwise, no interrupt is generated when an overrun error occurs. This bit must only be
enabled in master mode.
0 – Disable overrun error interrupts.
1 – Enable overrun error interrupts.
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Microwire/SPI Interface 223