CP3BT23_14 Datasheet, PDF (228/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an
acknowledge signal after every byte received. There are two exceptions to the “acknowledge after every
byte” rule.
• When the master is the receiver, it must indicate to the transmitter an end-of-data condition by not-
acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative
acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is
not pulled down.
• When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative
acknowledge to indicate that it cannot accept additional data bytes.
Addressing Transfer Formats
Each device on the bus has a unique address. Before any data is transmitted, the master transmits the
address of the slave being addressed. The slave device should send an acknowledge signal on the SDA
signal, once it recognizes its address.
The address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends
on the bit sent after the address (the eighth bit). A low-to-high transition during a SCL high period
indicates the Stop Condition, and ends the transaction (Figure 23-5).
SDA
SCL
S
1-7 8 9
Address R/W ACK
1-7 8 9
Data
ACK
1-7 8 9
P
Data
AC K
Start
Condition
Stop
Condition
DS079
Figure 23-5. A Complete ACCESS.bus Data Transaction
When the address is sent, each device in the system compares this address with its own. If there is a
match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state
of the R/W bit (1 = read, 0 = write), the device acts as a transmitter or a receiver.
The ACCESS.bus protocol allows sending a general call address to all slaves connected to the bus. The
first byte sent specifies the general call address (00h) and the second byte specifies the meaning of the
general call (for example, “Write slave address by software only”). Those slaves that require the data
acknowledge the call and become slave receivers; the other slaves ignore the call.
Arbitration on the Bus
Arbitration is required when multiple master devices attempt to gain control of the bus simultaneously.
Control of the bus is initially determined according to address bits and clock cycle. If the masters are trying
to address the same bus device, data comparisons determine the outcome of this arbitration. In master
mode, the device immediately aborts a transaction if the value sampled on the SDA lines differs from the
value driven by the device. (Exceptions to this rule are SDA while receiving data; in these cases the lines
may be driven low by the slave without causing an abort.)
The SCL signal is monitored for clock synchronization and allows the slave to stall the bus. The actual
clock period will be the one set by the master with the longest clock period or by the slave stall period.
The clock high period is determined by the master with the shortest clock high period.
When an abort occurs during the address transmission, the master that identifies the conflict should give
up the bus, switch to slave mode, and continue to sample SDA to see if it is being addressed by the
winning master on the ACCESS.bus.
228 ACCESS.bus Interface
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