CP3BT23_14 Datasheet, PDF (53/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
9.3.2 Double Buffer Operation
This mode allows software to set up the next block transfer while the current block transfer proceeds.
Initialization
1. Write the block transfer addresses and byte count into the ADCAn, ADCBn, and BLTCn counters.
2. Clear the DMACNTLn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing
a 1 to it.
3. Set the DMACNTLn.CHEN bit. This activates the channel and enables it to respond to DMA transfer
requests.
4. While the current block transfer proceeds, write the addresses and byte count for the next block into
the ADRAn, ADRBn, and BLTRn registers. The BLTRn register must be written last, because it sets
the DMASTAT.VLD bit which indicates that all the parameters for the next transfer have been updated.
Continuation/Termination
When the BLTCn counter reaches 0:
1. The DMASTAT.TC bit is set.
2. An interrupt is generated if enabled by the DMACNTLn.ETC bit.
3. The DMAC channel checks the value of the VLD bit.
If the DMASTAT.VLD bit is set:
1. The channel copies the ADRAn, ADRBn, and BLTRn values into the ADCAn, ADCBn, and BLTCn
registers.
2. The DMASTAT.VLD bit is cleared.
3. The next block transfer is started.
If the DMASTAT.VLD bit is clear:
1. The transfer operation terminates.
2. The channel sets the DMASTAT.OVR bit.
3. The DMASTAT.CHAC bit is cleared.
4. An interrupt is generated if enabled by the DMACNTLn.EOVR bit.
The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely
starting a new DMA transfer.
Note: The ADCBn and ADRBn registers are used only in indirect (memory-to-memory) transfer. In direct
(flyby) mode, the DMAC does not use them and therefore does not copy ADRBn into ADCBn.
9.3.3 Auto-Initialize Operation
This mode allows the DMAC to continuously fill the same memory area without software intervention.
Initialization
1. Write the block addresses and byte count into the ADCAn, ADCBn, and BLTCn counters, as well as
the ADRAn, ADRBn, and BLTRn registers.
2. Set the DMACNTLn.OT bit to select auto-initialize mode.
3. Set the DMACNTLn.CHEN bit to activate the channel and enable it to respond to DMA transfer
requests.
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