CP3BT23_14 Datasheet, PDF (221/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

www.ti.com
CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Figure 22-5. Alternate Mode (SCIDL = 0)
Figure 22-6. Alternate Mode (SCIDL = 1)
22.3 SLAVE MODE
In Slave mode, the MSK pin is an input for the shift clock MSK. MDIDO is placed in TRI-STATE mode
when MWCS is inactive. Data transfer is enabled when MWCS is active.
The slave starts driving MDIDO when MWCS is active. The most significant bit (lower byte in 8-bit mode
or upper byte in 16-bit mode) is output onto the MDIDO pin first. After eight or sixteen clocks (depending
on the selected mode), the data transfer is completed.
If a new shift process starts before MWDAT was written, i.e., while MWDAT does not contain any valid
data, and the ECHO bit is set, the data received from MDODI is transmitted on MDIDO in addition to being
shifted to MWDAT. If the ECHO bit is clear, the data transmitted on MDIDO is the data held in the
MWDAT register, regardless of its validity. The master may negate the MWCS signal to synchronize the
bit count between the master and the slave. In the case that the slave is the only slave in the system,
MWCS can be tied to ground.
22.4 INTERRUPT GENERATION
Interrupts may be enabled for any of the conditions shown in Table 22-1.
Condition
Not Busy
Read Buffer Full
Overrun
Table 22-1. Microwire Interrupt Trigger Condition
Status Bit in the MWSTAT Register
BSY
RBF
OVF
Interrupt Enable Bit
in the MWCTRL1
Register
EIW
EIR
EIO
Description
The shifter is ready for the next data transfer
sequence.
The read buffer is full and waiting to be
unloaded.
A new data transfer sequence started while
both the shifter and the read buffer were full.
Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CP3BT23
Microwire/SPI Interface 221