CP3BT23_14 Datasheet, PDF (77/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
12.5 HARDWARE CLOCK CONTROL
The Hardware Clock Control (HCC) mechanism gives the Bluetooth Lower Link Controller (LLC) individual
control over the high-frequency oscillator and the PLL. The Bluetooth LLC can enter a Sleep mode for a
specified number of low-frequency clock cycles. While the Bluetooth LLC is in Sleep mode and the
CP3BT23 is in Power Save or Idle mode, the HCC mechanism may be used to control whether the high-
frequency oscillator, PLL, or both units are disabled.
Altogether, three mechanisms control whether the high-frequency oscillator is active, and four
mechanisms control whether the PLL is active:
• HCC Bits: The HCCM and HCCH bits in the PMMCR register may be used to disable the high-
frequency oscillator and PLL, respectively, in Power Save and Idle modes when the Bluetooth LLC is
in Sleep mode.
• Disable Bits: The DMC and DHC bits in the PMMCR register may be used to disable the high-
frequency oscillator and PLL, respectively, in Power Save and Idle modes. When used to disable the
high-frequency oscillator or PLL, the DMC and DHC bits override the HCC mechanism.
• Power Management Mode: Halt mode disables the high-frequency oscillator and PLL. Active Mode
enables them. The DMC and DHC bits and the HCC mechanism have no effect in Active or Halt mode.
• PLL Power Down Bit: The PLLPWD bit in the CRCTRL register can be used to disable the PLL in all
modes. This bit does not affect the high-frequency oscillator.
12.6 POWER MANAGEMENT REGISTERS
Name
PMMCR
PMMSR
Table 12-3. Power Management Registers
Address
FF FC60h
FF FC62h
Description
Power Management Control Register
Power Management Status Register
12.6.1 Power Management Control Register (PMMCR)
The Power Management Control/Status Register (PMMCR) is a byte-wide, read/write register that controls
the operating power mode (Active, Power Save, Idle, or Halt) and enables or disables the high-frequency
oscillator in the Power Save and Idle modes. At reset, the non-reserved bits of this register are cleared.
The format of the register is shown below.
7
HCCH
6
HCCM
5
DHC
4
DMC
3
WBPSM
2
HALT
1
IDLE
0
PSM
PSM
IDLE
If the Power Save Mode bit is clear and the WBPSM bit is clear, writing 1 to the PSM bit
causes the device to start the switch to Power Save mode. If the WBPSM bit is set when
the PSM bit is written with 1, entry into Power Save mode is delayed until execution of a
WAIT instruction. The PSM bit becomes set after the switch to Power Save mode is
complete. The PSM bit can be cleared by software, and it can be cleared by hardware when
a hardware wake-up event is detected.
0 – Device is not in Power Save mode.
1 – Device is in Power Save mode.
The Idle Mode bit indicates whether the device has entered Idle mode. The WBPSM bit
must be set to enter Idle mode. When the IDLE bit is written with 1, the device enters IDLE
mode at the execution of the next WAIT instruction. The IDLE bit can be set and cleared by
software. It is also cleared by the hardware when a hardware wake-up event is detected.
0 – Device is not in Idle mode.
1 – Device is in Idle mode.
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