CP3BT23_14 Datasheet, PDF (177/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
FIFO Operation
When a complete data word has been transmitted through the STD pin, a new data word is reloaded from
the transmit FIFO from the current location of the Transmit FIFO Read Pointer (TRP). After that, the TRP
is automatically incremented by 1. Therefore, the audio data to be transmitted in the next slot of the frame
is read from the next FIFO location.
A write to the Audio Transmit FIFO Register (ATFR) results in a write to the transmit FIFO at the current
location of the Transmit FIFO Write Pointer (TWP). After every write operation to the transmit FIFO, the
TWP is automatically incremented by 1.
When the TRP is equal to the TWP and the last access to the FIFO was a read operation (transfer to the
ATSR), the transmit FIFO is empty. When an additional read operation from the FIFO to the ATSR is
performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this case, the read
pointer (TRP) will be decremented by 1 (incremented by 15) and the previous data word will be
transmitted again. A transmit FIFO underrun is indicated by the TXU bit in the Audio Interface Transmit
Status and Control Register (ATSCR). No transmit interrupt will be generated (even if enabled).
If the current TRP is equal to the TWP and the last access to the FIFO was a write operation (to the
ATFR), the FIFO is full. If an additional write to the ATFR is performed, a transmit FIFO overrun occurs.
This error condition is not prevented by hardware. Software must ensure that no transmit overrun occurs.
The transmit frame synchronization pulse on the SFS pin and the transmit shift clock on the SCK pin may
be generated internally, or they can be supplied by an external source.
19.5.8 Receive
The receive shift register (ARSR) receives data words of all slots in the frame, regardless of the slot
assignment of the interface. However, only those ARSR contents are transferred to the receive FIFO or
DMA receive register which were received during the assigned time slots. A receive interrupt or DMA
request is initiated when this occurs.
DMA Operation
When a complete data word has been received through the SRD pin in a slot n, the new data word is
transferred to the corresponding receive DMA register n (ARDRn). A DMA request is asserted when the
ARDRn register is full. If a new slot n data word is received while the ARDRn register is still full, the
ARDRn register will be overwritten with the new data.
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