CP3BT23_14 Datasheet, PDF (160/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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EIEN
IEN
The Error Interrupt Enable bit allows the CAN module to interrupt the CPU if any kind of CAN
receive/transmit errors are detected. This causes any error status change in the error counter
registers REC/TEC is able to generate an error interrupt.
0 – The error interrupt is disabled and no error interrupt will be generated.
1 – The error interrupt is enabled and a change in REC/TEC will cause an interrupt to be
generated.
The Buffer Interrupt Enable bits allow software to enable/disable the interrupt source for the
corresponding message buffer. For example, IEN14 controls interrupts from buffer14, and
IEN0 controls interrupts from buffer0.
0 – Buffer as interrupt source disabled.
1 – Buffer as interrupt source enabled.
18.10.11 CAN Interrupt Pending Register (CIPNDn)
The CIPNDn register indicates any CAN Receive/Transmit Interrupt Requests caused by the message
buffers 0..14 and CAN error occurrences.
15
14
0
EIPND
IPND
0
R
EIPND
IPND
The Error Interrupt Pending field indicates the status change of TEC/REC and will execute
an error interrupt if the EIEN bit is set. Software has the responsibility to clear the EIPND bit
using the CICLRn register.
0 – CAN status is not changed.
1 – CAN status is changed.
The Buffer Interrupt Pending bits are set by the CAN module following a successful
transmission or reception of a message to or from the corresponding message buffer. For
example, IPND14 corresponds to buffer14, and IPND0 corresponds to buffer0.
0 – No interrupt pending for the corresponding message buffer.
1 – Message buffer has generated an interrupt.
18.10.12 CAN Interrupt Clear Register (CICLRn)
The CICLRn register bits individually clear CAN interrupt pending flags caused by the message buffers
and from the Error Management Logic. Do not modify this register with instructions that access the
register as a read-modify-write operand, such as the bit manipulation instructions.
15
14
0
EICLR
ICLR
0
W
EICLR
ICLR
The Error Interrupt Clear bit is used to clear the EIPND bit.
0 – The EIPND bit is unaffected by writing 0.
1 – The EIPND bit is cleared by writing 1.
The Buffer Interrupt Clear bits are used to clear the IPND bits.
0 – The corresponding IPND bit is unaffected by writing 0.
0 – The corresponding IPND bit is cleared by writing 1.
160 CAN Module
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