CP3BT23_14 Datasheet, PDF (204/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
www.ti.com
The format shown in Figure 21-6 consists of one start bit, nine data bits, and one or two stop bits. This
format also supports the UART attention feature. When operating in this format, all eight bits of UnTBUF
and UnRBUF are used for data. The ninth data bit is transmitted and received using two bits in the control
registers, called UXB9 and URB9. Parity is not generated or verified in this mode.
Start
3
Bit
9-Bit Data
1S
Start
3a
Bit
9-Bit Data
2S
DS065
Figure 21-6. 9-bit Data Frame Options
21.2.6 Baud Rate Generator
The Baud Rate Generator creates the basic baud clock from the System Clock. The System Clock is
passed through a two-stage divider chain consisting of a 5-bit baud rate prescaler (UnPSC) and an 11-bit
baud rate divisor (UnDIV).
The relationship between the 5-bit prescaler select (UnPSC) setting and the prescaler factors is shown in
Table 21-1.
Prescaler Select
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
Table 21-1. Prescaler Factors
Prescaler Factor
No clock
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
204 UART Modules
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