CP3BT23_14 Datasheet, PDF (157/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
18.10.7 CAN Timing Register (CTIM)
The Can Timing Register (CTIM) defines the configuration of the Bit Time Logic (BTL).
15
PSC
9
8
7
6
SJW
0
R/W
TSEG1
3
2
0
TSEG2
PSC6:0
000000
000001
000010
000011
000100
:
1111101
1111110
1111111
Table 18-14. CAN Prescaler Settings
Prescaler
2
3
4
5
6
:
127
128
128
SJW
The Synchronization Jump Width field specifies the Synchronization Jump Width, which can
be programmed between 1 and 4 time quanta (see Table 18-15).
SJW
00
01
10
11
Table 18-15. SJW Settings
Synchronization Jump Width (SJW)
1 time quantum
2 time quanta
3 time quanta
4 time quanta
Note: The settings of SJW must be configured to be smaller or equal to TS
TSEG1
The Time Segment 1 field configures the length of the Time Segment 1 (TSEG1). It is not
recommended to configure the time segment 1 to be smaller than 2 time quanta. (see ).
EG1 and TSEG2
TSEG1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Table 18-16. Time Segment 1 Settings
Length of Time (TSEG1)
Not recommended
2 time quanta
3 time quanta
4 time quanta
5 time quanta
6 time quanta
7 time quanta
8 time quanta
9 time quanta
10 time quanta
11 time quanta
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CAN Module 157