CP3BT23_14 Datasheet, PDF (236/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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GCMEN
The Global Call Match Enable bit enables the match of an incoming address byte to the
general call address (Start Condition followed by address byte of 00h) while the ACB is in
slave mode. When cleared, the ACB does not respond to a global call.
0 – Global call matching disabled.
1 – Global call matching enabled.
NMINTE
The New Match Interrupt Enable controls whether ACB interrupts are generated on new
matches. Set the NMINTE bit to enable the interrupt on a new match (i.e., when
ACBST.NMATCH is set). The interrupt is issued only if the ACBCTL1.INTEN bit is set.
0 – New match interrupts disabled.
1 – New match interrupts enabled.
STASTRE
The Stall After Start Enable bit enables the stall after start mechanism. When enabled, the
ACB is stalled after the address byte. When the STASTRE bit is clear, the ACBST.STASTR
bit is always clear.
0 – No stall after start.
1 – Stall-after-start enabled.
23.3.5 ACB Control Register 2 (ACBCTL2)
The ACBCTL2 register is a byte-wide, read/write register that controls the module and selects the ACB
clock rate. At reset, the ACBCTL2 register is cleared.
7
1
0
SCLFRQ6:0
ENABLE
ENABLE
SCLFRQ
The Enable bit controls the ACB module. When this bit is set, the ACB module is enabled.
When the Enable bit is clear, the ACB module is disabled, the ACBCTL1, ACBST, and
ACBCST registers are cleared, and the clocks are halted.
0 – ACB module disabled.
1 – ACB module enabled.
The SCL Frequency field specifies the SCL period (low time and high time) in master mode.
The clock low time and high time are defined as follows:
tSCLl = tSCLh = 2 × SCLFRQ × tCLK
Where tCLK is this device’s clock period when in Active mode. The SCLFRQ field may be
programmed to values in the range of 0001000b through 1111111b. Using any other value
has unpredictable results.
23.3.6 ACB Control Register 3 (ACBCTL3)
The ACBCTL3 register is a byte-wide, read/write register that expands the clock prescaler field and
enables ARP matches. At reset, the ACBCTL3 register is cleared.
7
3
2
1
0
Reserved
ARPMEN
SCLFRQ8:7
ARPMEN
The ARP Match Enable bit enables the matching of an incoming address byte to the SMBus
ARP address 110 0001b general call address (Start condition followed by address byte of
00h), while the ACB is in slave mode.
0 – ACB does not respond to ARP addresses.
1 – ARP address matching enabled.
SCLFRQ The SCL Frequency field specifies the SCL period (low time and high time) in master mode.
The ACBCTL3 register provides a 2-bit expansion of this field, with the remaining 7 bits being
held in the ACBCTL2 register.
236 ACCESS.bus Interface
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