CP3BT23_14 Datasheet, PDF (268/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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IxBEN
IxCEN
IxDEN
The Timer x Interrupt B Enable bit controls interrupt requests triggered on the corresponding
IxBPD bit being set. The associated IxBPD bit will be updated regardless of the value of the
IxBEN bit.
0 – Disable system interrupt request for the IxBPD pending bit.
1 – Enable system interrupt request for the IxBPD pending bit.
The Timer x Interrupt C Enable bit controls interrupt requests triggered on the corresponding
IxCPD bit being set. The associated IxCPD bit will be updated regardless of the value of the
IxCEN bit.
0 – Disable system interrupt request for the IxCPD pending bit.
1 – Enable system interrupt request for the IxCPD pending bit.
Timer x Interrupt D Enable bit controls interrupt requests triggered on the corresponding
IxDPD bit being set. The associated IxDPD bit will be updated regardless of the value of the
IxDEN bit.
0 – Disable system interrupt request for the IxDPD pending bit.
1 – Enable system interrupt request for the IxDPD pending bit.
26.2.5 Interrupt Pending Register (INTPND)
The INTPND register is a word-wide read/write register which contains all 16 interrupt pending bits. There
are four interrupt pending bits called IxAPD through IxDPD for each timer subsystem. Each interrupt
pending bit is set by a hardware event and can be cleared if software writes a 1 to the bit position. The
value will remain unchanged if a 0 is written to the bit position. All interrupt pending bits are cleared (0)
upon reset.
7
I2DPD
6
I2CPD
5
I2BPD
4
I2APD
3
I1DPD
2
I1CPD
1
I1BPD
0
I1APD
15
I4DPD
14
I4CPD
13
I4BPD
12
I4APD
11
I3DPD
10
I3CPD
9
I3BPD
8
I3APD
IxAPD
The Timer x Interrupt A Pending bit indicates that an interrupt condition for the related timer
subsystem has occurred. Table 26-1 lists the hardware condition which causes this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
IxBPD
The Timer x Interrupt B Pending bit indicates that an interrupt condition for the related timer
subsystem has occurred. Table 26-1 lists the hardware condition which causes this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
IxCPD
The Timer x Interrupt C Pending bit indicates that an interrupt condition for the related timer
subsystem has occurred. Table 26-1 lists the hardware condition which causes this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
IxDPD
The Timer x Interrupt D Pending bit indicates that an interrupt condition for the related timer
subsystem has occurred. Table 26-1 lists the hardware condition which causes this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
268 Versatile Timer Unit (VTU)
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