CP3BT23_14 Datasheet, PDF (174/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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19.5 AUDIO INTERFACE OPERATION
19.5.1 Clock Configuration
The Aux1 clock (generated by the Clock module described in Section 11.9) must be configured, because it
is the time base for the AAI module. Software must write an appropriate divisor to the ACDIV1 field of the
PRSAC register to provide a 12 MHz input clock. Software also must enable the Aux1 clock by setting the
ACE1 bit in the CRCTRL register.
For example:
PRSAC &= 0xF0;
// Set Aux1 prescaler to 1 (F = 12 MHz)
CRCTRL |= ACE1; // Enable Aux1 clk
19.5.2 Interrupts
The interrupt logic of the AAI combines up to four interrupt sources and generates one interrupt request
signal to the Interrupt Control Unit (ICU).
The four interrupt sources are:
• RX FIFO Overrun ASCR.RXEIP = 1
• RX FIFO Almost Full (Warning Level) ASCR.RXIP = 1
• TX FIFO Under run ASCR.TXEIP = 1
• TX FIFO Almost Empty (Warning Level) ASCR.TXIP=1
In addition to the dedicated input to the ICU for handling these interrupt sources, the Serial Frame Sync
(SFS) signal is an input to the MIWU (see Section 13), which can be programmed to generate edge-
triggered interrupts.
Figure 19-6 shows the interrupt structure of the AAI.
RXIE
RXIP = 1
RXEIE
RXEIP = 1
TXIE
AAI
Interrupt
TXIP = 1
TXEIE
TXEIP = 1
DS155
Figure 19-6. AAI Interrupt Structure
174 Advanced Audio Interface
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