CP3BT23_14 Datasheet, PDF (98/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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RFDATA
The RFDATA signal is the multiplexed Bluetooth data receive and transmit signal. The data is provided at
a bit rate of 1 Mbit/s with 12× oversampling, synchronized to the 12 MHz BBCLK. The RFDATA signal is a
dedicated RF interface pin. This signal is driven to a logic high level after reset.
RFSYNC
In receive mode (data direction from the radio chip to the CP3BT23), the RFSYNC signal acts as the
frequency correction/DC compensation circuit control output to the radio chip. The RFSYNC signal is
driven low throughout the correlation phase and driven high when synchronization to the received access
code is achieved.
In transmit mode (data direction from the CP3BT23 to the radio chip), the RFSYNC signal enables the RF
output of the radio chip. When the RFSYNC pin is driven high, the RF transmitter circuit of the radio chip
is enabled, corresponding to the settings of the power control register in the radio chip.
The RFSYNC signal is the alternate function of the generalpurpose I/O pin PG0. At reset, this pin is in
TRI-STATE mode. Software must enable the alternate function of the PG0 pin to give control over this
signal to the RF interface.
RFCE
The RFCE signal is the chip enable output to the external RF chip. When the RFCE signal is driven high,
the RF chip power is controlled by the settings of its power control registers. When the RFCE signal is
driven low, the RF chip is powered-down. However, the serial interface is still operational and the
CP3BT23 can still access the RF chip internal control registers.
The RFCE signal is the alternate function of the generalpurpose I/O pin PG1. At reset, this pin is in TRI-
STATE mode. Software must enable the alternate function of the PG1 pin to give control over this signal
to the RF interface.
During Bluetooth power-down phases, the CP3BT23 provides a mechanism to reduce the power
consumption of an external RF chip by driving the RFCE signal of the RF interface to a logic low level.
This feature is available when the Power Management Module of the CP3BT23 has enabled the Hardware
Clock Control mechanism.
SCLK
The SCLK signal is the serial interface shift clock output. The CP3BT23 always acts as the master of the
serial interface and therefore always provides the shift clock. The SCLK signal is the alternate function of
the general-purpose I/O pin PG3. At reset, this pin is in TRI-STATE mode. Software must enable the
alternate function of the PG3 pin to give control over this signal to the RF interface.
SDAT
The SDAT signal is the multiplexed serial data receive and transmit path between the radio chip and the
CP3BT23.clock signal. The radio chip uses this signal internally as the 12× oversampling clock and
provides it externally to the CP3BT23 for use as the Main Clock.
The SDAT signal is the alternate function of the general-purpose I/O pin PG4. At reset, this pin is in TRI-
STATE mode. Software must enable the alternate function of the PG4 pin to give control over this signal
to the RF interface.
SLE
The SLE pin is the serial load enable output of the serial interface of the CP3BT23.
During write operations (to the radio chip registers), the data received by the shift register of the radio chip
is copied into the address register on the next rising edge of SCLK after the SLE signal goes high.
During read operations (read from the registers), the radio chip releases the SDAT line on the next rising
edge of SCLK after the SLE signal goes high.
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Bluetooth Controller
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