CP3BT23_14 Datasheet, PDF (55/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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Name
ADCA1
ADRA1
ADCB1
ADRB1
BLTC1
BLTR1
DMACNTL1
DMASTAT1
ADCA2
ADRA2
ADCB2
ADRB2
BLTC2
BLTR2
DMACNTL2
DMASTAT2
ADCA3
ADRA3
ADCB3
ADRB3
BLTC3
BLTR3
DMACNTL3
DMASTAT3
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Table 9-2. DMA Controller Registers (continued)
Address
FF F820h
FF F824h
FF F828h
FF F82Ch
FF F830h
FF F834h
FF F83Ch
FF F83Eh
FF F840h
FF F844h
FF F848h
FF F84Ch
FF F850h
FF F854h
FF F85Ch
FF F85Eh
FF F860h
FF F864h
FF F868h
FF F86Ch
FF F870h
FF F874h
FF F87Ch
FF F87Eh
Description
Device A Address Counter Register
Device A Address Register
Device B Address Counter Register
Device B Address Register
Block Length Counter Register
Block Length Register
DMA Control Register
DMA Status Register
Device A Address Counter Register
Device A Address Register
Device B Address Counter Register
Device B Address Register
Block Length Counter Register
Block Length Register
DMA Control Register
DMA Status Register
Device A Address Counter Register
Device A Address Register
Device B Address Counter Register
Device B Address Register
Block Length Counter Register
Block Length Register
DMA Control Register
DMA Status Register
9.6.1 Device A Address Counter Register (ADCAn)
The Device A Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address
of either the source data item or the destination location, depending on the state of the DIR bit in the
CNTLn register. The ADA bit of DMACNTLn register controls whether to adjust the pointer in the ADCAn
register by the step size specified in the INCA field of DMACNTLn register. The upper 8 bits of the ADCAn
register are reserved and always clear.
31
24
23
0
Reserved
Device A Address Counter
9.6.2 Device A Address Register (ADRAn)
The Device A Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either
the next source data block, or the next destination data area, according to the DIR bit in the DMACNTLn
register. The upper 8 bits of the ADRAn register are reserved and always clear.
31
24
23
0
Reserved
Device A Address
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