CP3BT23_14 Datasheet, PDF (189/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
TXSA Bit
TXSA0
TXSA1
TXSA2
TXSA3
Table 19-6.
Slots Enabled
0
1
2
3
After reset, the TXSA field is clear, so software must load the correct slot assignment.
TXDSA
The Transmit DMA Slot Assignment field specifies which slots (audio channels) are
supported by DMA. If the TXDSA bit is set for an assigned slot n (TXSAn = 1), the data to be
transmitted within this slot will not be read from the transmit FIFO, but will instead be read
from the corresponding Transmit DMA data register (ATDRn). A DMA request n is asserted
when the ATDRn is empty. If the TSA bit for a slot is clear, the TXDSA bit is ignored. The
following table shows the DMA slot assignment scheme.
TXDSA Bit
TXDSA0
TXDSA1
TXDSA2
TXDSA3
Table 19-7.
Slots Enabled for DMA
0
1
2
3
TFWL
The Transmit FIFO Warning Level field specifies when a transmit interrupt is asserted. A
transmit interrupt is asserted when the number of bytes or words in the transmit FIFO is
equal or less than the warning level value. A TXFWL value of Fh means that a transmit
interrupt is asserted if one or more bytes or words are available in the transmit FIFO. At
reset, the TXFWL field is loaded with Fh.
19.7.9 Audio Clock Control Register (ACCR)
The ACCR register is used to control the bit timing of the audio interface. After reset, this register is clear.
7
1
0
FCPRS
CSS
15
CSS
FCPRS
BCPRS
8
BCPRS
The Clock Source Select bit selects one out of two possible clock sources for the audio
interface. After reset, the CSS bit is clear.
0 – The Auxiliary Clock 1 is used to clock the Audio Interface.
1 – The 48-MHz clock is used to clock the Audio Interface.
The Frame Clock Prescaler is used to divide the bit clock to generate the frame clock for the
receive and transmit operations. The bit clock is divided by (FCPRS + 1). After reset, the
FCPRS field is clear. The maximum allowed bit clock rate to achieve an 8 kHz frame clock is
1024 kHz. This value must be set correctly even if the frame sync is generated externally.
The Bit Clock Prescaler is used to divide the audio interface clock (selected by the CSS bit)
to generate the bit clock for the receive and transmit operations. The audio interface input
clock is divided by (BCPRS + 1). After reset, the BCPRS[7:0] bits are clear.
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Advanced Audio Interface 189