HD6413007F20 Datasheet, PDF (86/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

2. CPU
T₁
T₂
φ
Address bus
Address
AS, RD, HWR, LWR
D₁₅ to D₀
High
High impedance
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
Bus cycle
T₁ state
T₂ state
T₃ state
φ
Address bus
Address
Read
access
Internal read signal
Internal data bus
Read data
Write
access
Internal write signal
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
Rev.5.00 Sep. 12, 2007 Page 56 of 764
REJ09B0396-0500