HD6413007F20 Datasheet, PDF (388/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
10.2.4 Timer Control Register (8TCR)
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
8TCR is an 8-bit readable/writable register that selects the input clock source and the time at
which 8TCNT is cleared, and enables interrupts.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 10.4, Operation.
Bit 7⎯Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB
0
1
Description
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
(Initial value)
Bit 6⎯Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA
0
1
Description
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
(Initial value)
Bit 5⎯Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt
request when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE
0
1
Description
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 358 of 764
REJ09B0396-0500