HD6413007F20 Datasheet, PDF (448/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
12.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST RSTOE ⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)* R/W
⎯
⎯
⎯
⎯
⎯
⎯
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on
Register Access.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7⎯Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3006 and
H8/3007 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO
pin to initialize external system devices.
Bit 7
WRST
0
1
Description
[Clearing condition]
Reset signal at RES pin.
Read WRST when WRST =1, then write 0 in WRST.
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Rev.5.00 Sep. 12, 2007 Page 418 of 764
REJ09B0396-0500