HD6413007F20 Datasheet, PDF (428/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
Address H'FFFA6
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯ NDR11 NDR10 NDR9 NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Reserved bits
11.2.7 Next Data Enable Register A (NDERA)
Next data 11 to 8
These bits store the next output
data for TPC output group 2
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP₇ to TP₀) on a bit-by-bit basis.
Bit
Initial value
Read/Write
7
NDER7
0
R/W
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0⎯Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP₇ to TP₀) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
0
1
Description
TPC outputs TP₇ to TP₀ are disabled
(NDR7 to NDR0 are not transferred to PA₇ to PA₀)
TPC outputs TP₇ to TP₀ are enabled
(NDR7 to NDR0 are transferred to PA₇ to PA₀)
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 398 of 764
REJ09B0396-0500