HD6413007F20 Datasheet, PDF (391/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
10.2.5 Timer Control/Status Registers (8TCSR)
8TCSR0
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
8TCSR2
Bit
Initial value
Read/Write
7
6
5
4
CMFB CMFA OVF
⎯
0
0
0
1
R/(W)* R/(W)* R/(W)* ⎯
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
8TCSR1, 8TCSR3
Bit
7
6
5
4
3
CMFB CMFA OVF
ICE
OIS3
Initial value
0
0
0
0
0
Read/Write
R/(W)* R/(W)* R/(W)* R/W R/W
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
The timer control/status registers (8TCSR) are 8-bit registers that indicate compare match/input
capture and timer overflow statuses, and control compare match output/input capture edge
selection.
Each 8TCSR is initialized to H'00 by a reset and in standby mode.
Rev.5.00 Sep. 12, 2007 Page 361 of 764
REJ09B0396-0500