HD6413007F20 Datasheet, PDF (105/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

4. Exception Handling
4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ₀ to IRQ₅), and
36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication
interface (SCI), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts
NMI (1)
IRQ₀ to IRQ₅ (6)
Internal interrupts
WDT*¹ (1)
DRAM interface*² (1)
16-bit timer (9)
8-bit timer (8)
DMAC (4)
SCI (12)
A/D converter (1)
Notes: Numbers in parentheses are the number of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
2. When the DRAM interface is used as an interval timer, it generates an interrupt request
at compare match.
Figure 4.4 Interrupt Sources and Number of Interrupts
Rev.5.00 Sep. 12, 2007 Page 75 of 764
REJ09B0396-0500