HD6413007F20 Datasheet, PDF (782/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must r⊕emain
low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
RES
t₁ ≥ 10t_cyc
t₂ ≥ 0 ns
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
t ≥ 100 ns
t_OSC
Rev.5.00 Sep. 12, 2007 Page 752 of 764
REJ09B0396-0500