HD6413007F20 Datasheet, PDF (251/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.4.6 Block Transfer Mode
In block transfer mode, the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 7.10 indicates the register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
0
MARA
23
0
MARB
7
0
ETCRAH
7
0
ETCRAL
Function
Initial Setting
Operation
Source address
register
Transfer source
start address
Incremented or
decremented once per
transfer, or held fixed
Destination
address register
Transfer destination Incremented or
start address
decremented once per
transfer, or held fixed
Block size counter Block size
Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRL
Initial block size Block size
Held fixed
15
ETCRB
0 ^{Block transfer}
counter
Legend:
MARA:
MARB:
ETCRA:
ETCRB:
Memory address register A
Memory address register B
Execute transfer count register A
Execute transfer count register B
Number of block
transfers
Decremented once per
block transfer until H'0000
is reached and the
transfer ends
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
Rev.5.00 Sep. 12, 2007 Page 221 of 764
REJ09B0396-0500