HD6413007F20 Datasheet, PDF (156/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Bit 4⎯Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
0
1
Description
Refresh cycles disabled
DRAM refresh cycles enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (Tp) is to
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit
does not affect the self-refresh function.
Bit 2
TPC
0
1
Description
1-state precharge cycle inserted
2-state precharge cycle inserted
(Initial value)
Bit 1⎯RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between T_r and T_c1 in DRAM
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW
0
1
Description
Wait state (Trw) insertion disabled
One wait state (Trw) inserted
(Initial value)
Bit 0⎯Refresh Cycle Wait Control (RLW): Controls wait state (T_RW) insertion for CAS-before-
RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW
0
1
Description
Wait state (T_RW) insertion disabled
One wait state (T ) inserted
RW
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 126 of 764
REJ09B0396-0500