HD6413007F20 Datasheet, PDF (249/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Figure 7.8 illustrates how normal mode operates.
Address T_A
Transfer
7. DMA Controller
Address T _B
Address B_A
Address B_B
Legend:
L _A = initial setting of MARA
L _B = initial setting of MARB
N = initial setting of ETCRA
T_A = L_A
B_A = L_A + SAIDE • (−1)^SAID • (2 ^DTSZ • N − 1)
T_B = L_B
B_B = L_B + DAIDE • (−1)^DAID • (2 ^DTSZ • N − 1)
Figure 7.8 Operation in Normal Mode
Transfers can be requested (activated) by an external request or auto-request. An auto-requested
transfer is activated by the register settings alone. The designated number of transfers are executed
automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode, the DMAC
releases the bus temporarily after each transfer. In burst mode, the DMAC keeps the bus until the
transfers are completed, unless there is a bus request from a higher-priority bus master.
For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
Rev.5.00 Sep. 12, 2007 Page 219 of 764
REJ09B0396-0500