HD6413007F20 Datasheet, PDF (119/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

5. Interrupt Controller
Bit 2⎯Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2
0
1
Description
SCI channel 1 interrupt requests have priority level 0 (low priority)
SCI channel 1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 1⎯Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.
Bit 1
IPRB1
0
1
Description
SCI channel 2 interrupt requests have priority level 0 (low priority)
SCI channel 2 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 0⎯Reserved: This bit can be written and read, but it does not affect interrupt priority.
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ₀ to IRQ₅ interrupt
requests.
Bit
7
⎯
Initial value
0
Read/Write
⎯
6
5
4
3
2
1
0
⎯ IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
⎯ R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Reserved bits
IRQ ₅ to IRQ₀ flags
These bits indicate IRQ ₅ to IRQ₀
interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can not be modified and are always read as 0.
Rev.5.00 Sep. 12, 2007 Page 89 of 764
REJ09B0396-0500