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HD6413007F20 Datasheet, PDF (334/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
9. 16-Bit Timer
Bit 4⎯Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the
OVF0 flag when OVF0 is set to 1.
Bit 4
OVIE0
0
1
Description
OVI0 interrupt requested by OVF0 flag is disabled
OVI0 interrupt requested by OVF0 flag is enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow.
Bit 2
OVF2
Description
0
[Clearing condition]
Read OVF2 when OVF2 =1, then write 0 in OVF2.
(Initial value)
1
[Setting condition]
16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF.
Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow
occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
Bit 1⎯Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow.
Bit 1
OVF1
0
1
Description
[Clearing condition]
Read OVF1 when OVF1 =1, then write 0 in OVF1.
[Setting condition]
16TCNT1 overflowed from H'FFFF to H'0000.
(Initial value)
Bit 0⎯Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.
Bit 0
OVF0
0
1
Description
[Clearing condition]
Read OVF0 when OVF0 =1, then write 0 in OVF0.
[Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000.
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 304 of 764
REJ09B0396-0500