HD6413007F20 Datasheet, PDF (426/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
7
6
5
4
3
2
1
0
NDR7 NDR6 NDR5 NDR4 ⎯
⎯
⎯
⎯
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
Address H'FFFA7
Bit
7
⎯
Initial value
1
Read/Write
⎯
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
6
5
4
3
2
1
0
⎯
⎯
⎯
NDR3 NDR2 NDR1 NDR0
1
1
1
0
0
0
0
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Reserved bits
11.2.6 Next Data Register B (NDRB)
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP₁₅ to TP₈). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev.5.00 Sep. 12, 2007 Page 396 of 764
REJ09B0396-0500