HD6413007F20 Datasheet, PDF (138/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
• Burst ROM interface
⎯ Burst ROM interface can be set for area 0
⎯ Selection of two- or three-state burst access
• Idle cycle insertion
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
• Bus arbitration function
⎯ A built-in bus arbiter grants the bus right to the CPU, DMAC, DRAM interface, or an
external bus master
• Other features
⎯ The refresh counter (refresh timer) can be used as an interval timer
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
Rev.5.00 Sep. 12, 2007 Page 108 of 764
REJ09B0396-0500