HD6413007F20 Datasheet, PDF (623/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

20. Electrical Characteristics
φ
NMI
IRQ _E
IRQ _L
t_NMIS t_NMIH
t_NMIS t_NMIH
t_NMIS
IRQ _E: Edge-sensitive IRQ _i
IRQ _L : Level-sensitive IRQ _i (i = 0 to 5)
NMI
t_NMIW
IRQ _j
(j = 0 to 5)
Figure 20.7 Interrupt Input Timing
20.3.3 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 20.8 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 20.9 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 20.10 shows the timing of the external three-state access cycle with one wait state
inserted.
• Burst ROM access timing: burst cycle two-state
Figure 20.11 shows the timing of the burst cycle two-state access.
• Burst ROM access timing: burst cycle three-state
Figure 20.12 shows the timing of the burst cycle three-state access.
• Bus-release mode timing
Figure 20.13 shows the bus-release mode timing.
Rev.5.00 Sep. 12, 2007 Page 593 of 764
REJ09B0396-0500