HD6413007F20 Datasheet, PDF (193/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
The H8/3006 and H8/3007 have a function that places the DRAM in self-refresh mode when the
chip enters software standby mode.
To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction is
subsequently executed in order to enter software standby mode, the CAS and RAS signals are
output and the DRAM enters self-refresh mode, as shown in figure 6.28.
When the chip exits software standby mode, CAS and RAS outputs go high.
The following conditions must be observed when the self-refresh function is used:
• When burst access is selected, RAS up mode must be selected before executing a SLEEP
instruction in order to enter software standby mode. Therefore, if RAS down mode has been
selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before
executing the SLEEP instruction. Select RAS down mode again after exiting software standby
mode.
• The instruction immediately following a SLEEP instruction must not be located in an area
designated as DRAM space.
The self-refresh function will not work properly unless the above conditions are observed.
φ
Address bus
CSn(RAS)
Software standby Oscillation stabilization
mode
time
High-impedance
PB4(UCAS)
PB5(LCAS)
RD(WE)
RFSH
Figure 6.28 Self-Refresh Timing (CSEL = 0)
Rev.5.00 Sep. 12, 2007 Page 163 of 764
REJ09B0396-0500