HD6413007F20 Datasheet, PDF (402/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
10.4.4 Timing of Status Flag Setting
Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in
8TCSR are set to 1 by the compare match signal output when the TCOR and 8TCNT values
match. The compare match signal is generated in the last state of the match (when the matched
8TCNT count value is updated). Therefore, after the 8TCNT and TCOR values match, the
compare match signal is not generated until an incrementing clock pulse is generated. Figure 10.14
shows the timing in this case.
φ
8TCNT
N
TCOR
N
Compare match signal
N+1
CMF
Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 10.15 shows the timing in this case.
φ
8TCNT
TCORB
Input capture signal
N
N
CMFB
Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs
Rev.5.00 Sep. 12, 2007 Page 372 of 764
REJ09B0396-0500