HD6413007F20 Datasheet, PDF (412/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, counter clearing by
the input capture signal takes priority and the counter is not incremented. The value before the
counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case.
T1
T2
T3
φ
Input capture signal
Counter clear signal
8TCNT internal clock
8TCNT
N
H'00
TCORB
X
N
Figure 10.22 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev.5.00 Sep. 12, 2007 Page 382 of 764
REJ09B0396-0500