HD6413007F20 Datasheet, PDF (527/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

14. Smart Card Interface
No parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Output from transmitting device
Parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Output from transmitting device
Legend:
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Output from
receiving
device
Figure 14.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
up resistor.
2. The transmitting device starts transfer of one frame of data. The data frame starts with a start
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
3. With the smart card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up resistor.
4. The receiving device carries out a parity check. If there is no parity error and the data is
received normally, the receiving device waits for reception of the next data. If a parity error
occurs, however, the receiving device outputs an error signal (DE, low-level) to request
retransmission of the data. After outputting the error signal for the prescribed length of time,
the receiving device places the signal line in the high-impedance state again. The signal line is
pulled high again by a pull-up resistor.
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data
frame. If it receives an error signal, however, it returns to step 2 and transmits the same data
again.
Rev.5.00 Sep. 12, 2007 Page 497 of 764
REJ09B0396-0500