HD6413007F20 Datasheet, PDF (432/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
Bits 1 and 0⎯Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP₃ to TP₀).
Bit 1
G0CMS1
0
1
Bit 0
G0CMS0
0
1
0
1
Description
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in 16-bit
timer channel 0
TPC output group 0 (TP to TP ) is triggered by compare match in 16-bit
3
0
timer channel 1
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in 16-bit
timer channel 2
TPC output group 0 (TP₃ to TP₀) is triggered by
compare match in 16-bit timer channel 2
(Initial value)
11.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯ G3NOV G2NOV G1NOV G0NOV
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W R/W R/W R/W
Reserved bits
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP₁₅ to TP₁₂)
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP₁₁ to TP₈ )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP₇ to TP₄ )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP₃ to TP₀ )
Rev.5.00 Sep. 12, 2007 Page 402 of 764
REJ09B0396-0500