HD6413007F20 Datasheet, PDF (712/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
TISRB⎯Timer Interrupt Status Register B H'FFF65
16-Bit Timer (Common)
Bit 7
6
5
4
3
2
1
0
⎯ IMIEB2 IMIEB1 IMIEB0 ⎯ IMFB2 IMFB1 IMFB0
Initial value 1
0
0
0
1
0
0
0
Read/Write ⎯ R/W R/W R/W ⎯ R/(W)* R/(W)* R/(W)*
Input capture/compare match flag B0
[Clearing condition]
(Initial value)
0 _{Read IMFB0 when IMFB0 =1, then write 0 in IMFB0}
[Setting conditions]
• 16TCNT0 = GRB0 when GRB0 functions as an
output compare register.
1 _{• 16TCNT0 value is transferred to GRB0 by an input}
capture signal when GRB0 functions as an input
capture register.
Input capture/compare match flag B1
0
[Clearing condition]
(Initial value)
Read IMFB1 when IMFB1 =1, then write 0 in IMFB1
[Setting conditions]
• 16TCNT1 = GRB1 when GRB1 functions as an output
1
compare register
• 16TCNT1 value is transferred to GRB1 by an input capture
signal when GRB1 functions as an input capture register
Input capture/compare match flag B2
0 ^{[Clearing condition]}
(Initial value)
Read IMFB2 when IMFB2 =1, then write 0 in IMFB2
[Setting conditions]
• 16TCNT2 = GRB2 when GRB2 functions as an output
1
compare register
• 16TCNT2 value is transferred to GRB2 by an input capture
signal when GRB2 functions as an input capture register
Input capture/compare match interrupt enable B0
0 IMIB0 interrupt requested by IMFB0 flag is disabled (Initial value)
1 IMIB0 interrupt requested by IMFB0 flag is enabled
Input capture/compare match interrupt enable B1
0 IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value)
1 IMIB1 interrupt requested by IMFB1 flag is enabled
Input capture/compare match interrupt enable B2
0 IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value)
1 IMIB2 interrupt requested by IMFB2 flag is enabled
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 682 of 764
REJ09B0396-0500