HD6413007F20 Datasheet, PDF (182/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.5.8 Wait Control
In a DRAM access cycle, wait states can be inserted (1) between the T_r state and T_c1 state, and (2)
between the T_c1 state and T_c2 state.
Insertion of T_rw Wait State between T_r and T_c1: One T_rw state can be inserted between T_r and T_c1
by setting the RCW bit to 1 in DRCRB.
Insertion of T_w Wait State(s) between T_c1 and T_c2: When the bit in ASTCR corresponding to an
area designated as DRAM space is set to 1, from 0 to 3 T_w states can be inserted between the T_c1
state and T_c2 state by means of settings in WCRH and WCRL.
Figure 6.18 shows an example of the timing for wait state insertion.
The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh
cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
φ
A23 to A0
AS
CSn(RAS)
Tp
Tr Trw Tc1 Tw
Tw Tc2
Row
Column
High
Read access
PB4 /PB5
(UCAS /LCAS)
RD(WE)
D15 to D0
High
Read data
Write access
PB4 /PB5
(UCAS /LCAS)
RD(WE)
D15 to D0
Write data
Note: n = 2 to 5
Figure 6.18 Example of Wait State Insertion Timing (CSEL = 0)
Rev.5.00 Sep. 12, 2007 Page 152 of 764
REJ09B0396-0500