HD6413007F20 Datasheet, PDF (163/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH/WCRL
ABWn ASTn Wn1 Wn0
0
0
⎯
⎯
1
0
0
1
1
0
1
1
0
⎯
⎯
1
0
0
1
1
0
1
Bus Specifications (Basic Bus Interface)
Bus Width Access States
Program Wait States
16
2
0
3
0
1
2
3
8
2
0
3
0
1
2
3
6.3.3 Memory Interfaces
The H8/3006 and H8/3007 memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst
ROM interface is designated functions as burst ROM space.
6.3.4 Chip Select Signals
For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS₀ to CS₇) that
goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn
signal.
Output of CS₀ to CS₃: Output of CS₀ to CS₃ is enabled or disabled in the data direction register
(DDR) of the corresponding port.
A reset leaves pin CS₀ in the output state and pins CS₁ to CS₃ in the input state. To output chip
select
signals
CS
1
to
CS₃,
the
corresponding
DDR
bits
must
be
set
to
1.
For
details,
see
section
8,
I/O Ports.
Rev.5.00 Sep. 12, 2007 Page 133 of 764
REJ09B0396-0500