HD6413007F20 Datasheet, PDF (195/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Connection Examples
• Figure 6.29 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs
using a × 16-bit organization, and the corresponding address map. The DRAMs used in this
example are of the 10-bit row address × 10-bit column address type. Up to four DRAMs can be
connected by designating areas 2 to 5 as DRAM space.
H8/3006 and H8/3007
CS2 (RAS2)
CS3 (RAS3)
PB4 (UCAS)
PB5(LCAS)
RD (WE)
A10-A1
2-CAS 16-Mbit DRAM
10-bit row address × 10-bit column address
× 16-bit organization
RAS
UCAS
LCAS
WE
No.1
A9-A0
D15-D0
D15-D0
OE
RAS
UCAS
LCAS
WE
No.2
A9-A0
D15-D0
OE
(a) Interconnections (example)
Area 2
Area 3
Area 4
Area 5
PB4
(UCAS)
15
H'400000
PB5
(LCAS)
87
0
H'5FFFFE
H'600000
H'7FFFFE
H'800000
DRAM (No. 1)
DRAM (No. 2)
H'9FFFFE
H'A00000
Normal
Normal
H'BFFFFE
CS2 (RAS2)
CS3 (RAS3)
CS4
CS5
(b) Address map
Figure 6.29 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with × 16-Bit
Organization
Rev.5.00 Sep. 12, 2007 Page 165 of 764
REJ09B0396-0500