HD6413007F20 Datasheet, PDF (319/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Clock selector
Comparator
Control logic
9. 16-Bit Timer
TIOCA₂
TIOCB₂
IMIA2
IMIB2
OVI2
Module data bus
Legend:
16TCNT2: Timer counter 2 (16 bits)
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
16TCR2:
Timer control register 2 (8 bits)
TIOR2:
Timer I/O control register 2 (8 bits)
Figure 9.3 Block Diagram of Channel 2
Rev.5.00 Sep. 12, 2007 Page 289 of 764
REJ09B0396-0500