HD6413007F20 Datasheet, PDF (214/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
CPU cycles
External bus released CPU cycles
T0
T1
T2
φ
Address bus
Data bus
AS
Address
High-impedance
High-impedance
High-impedance
RD
HWR, LWR
BREQ
High
High-impedance
High-impedance
BACK
Minimum 3 cycles
(1)
(2)
(3)
(4)
(5)
(6)
Figure 6.46 Example of External Bus Master Operation
In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.34).
When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before
executing the SLEEP instruction.
Rev.5.00 Sep. 12, 2007 Page 184 of 764
REJ09B0396-0500