HD6413007F20 Datasheet, PDF (246/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a
24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper
16 bits are all 1s. IOAR is not incremented or decremented.
Figure 7.6 illustrates how repeat mode operates.
Address T
Transfer
1 byte or word is
transferred per request
IOAR
Address B
Legend:
L = initial setting of MAR
N = initial setting of ETCRH and ETCRL
Address T = L
Address B = L + (−1)^DTID • (2^DTSZ • N − 1)
Figure 7.6 Operation in Repeat Mode
The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
Rev.5.00 Sep. 12, 2007 Page 216 of 764
REJ09B0396-0500