HD6413007F20 Datasheet, PDF (435/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
Table 11.3 TPC Operating Conditions
NDER
0
1
DDR
0
1
0
1
Pin Function
Generic input port
Generic output port
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
TPC pulse output
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 11.3.4, Non-Overlapping TPC Output.
11.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
16TCNT
GRA
Compare
match A signal
NDRB
N
N+1
N
n
PBDR
m
n
TP₈ to TP₁₅
m
n
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Rev.5.00 Sep. 12, 2007 Page 405 of 764
REJ09B0396-0500