HD6413007F20 Datasheet, PDF (258/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
CPU cycle
DMAC cycle (1 word transfer)
CPU cycle
φ
Address
bus
RD
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ T₁ T₂
Source
address
Destination address
HWR
LWR
Figure 7.13 DMA Transfer Bus Timing (Example)
Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
DMAC cycle
CPU cycle
DMAC cycle
(last transfer cycle)
CPU cycle
T₁ T₂ T₃ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
φ
DREQ
Address
bus
RD
HWR , LWR
TEND
Source Destination
address address
Source Destination
address address
Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
Rev.5.00 Sep. 12, 2007 Page 228 of 764
REJ09B0396-0500