HD6413007F20 Datasheet, PDF (120/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

5. Interrupt Controller
Bits 5 to 0⎯IRQ₅ to IRQ₀ Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ₅ to
IRQ₀ interrupt requests.
Bits 5 to 0
IRQ5F to IRQ0F Description
0
[Clearing conditions]
(Initial value)
• 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
• IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried
out.
• IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ₀ to IRQ₅ interrupt requests.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯ IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W
Reserved bits
IRQ ₅ to IRQ₀ enable
These bits enable or disable IRQ ₅ to IRQ ₀ interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0⎯IRQ₅ to IRQ₀ Enable (IRQ5E to IRQ0E): These bits enable or disable
IRQ₅ to IRQ₀ interrupts.
Bits 5 to 0
IRQ5E to IRQ0E Description
0
IRQ₅ to IRQ₀ interrupts are disabled
1
IRQ₅ to IRQ₀ interrupts are enabled
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 90 of 764
REJ09B0396-0500