HD6413007F20 Datasheet, PDF (139/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

CS0 to CS7
Internal address bus
Area
decoder
Chip select
control signals
ABWCR
ASTCR
BCR
CSCR
Bus control
circuit
6. Bus Controller
Internal signals
Bus mode control signal
Bus size control signal
Access state control signal
Wait request signal
WAIT
Internal signals
CPU bus request signal
DMAC bus request signal
DRAM interface bus request signal
CPU bus acknowledge signal
DMAC bus acknowledge signal
DRAM interface bus acknowledge signal
Wait state
controller
WCRH
WCRL
BRCR
Bus arbiter
BACK
BREQ
DRAM interface
DRAM control
Legend:
ABWCR : Bus width control register
ASTCR : Access state control register
WCRH : Wait control register H
WCRL : Wait control register L
BRCR : Bus release control register
CSCR : Chip select control register
DRCRA : DRAM control register A
DRCRB : DRAM control register B
RTMCSR : Refresh timer control/status register
RTCNT : Refresh timer counter
RTCOR : Refresh time constant register
BCR
: Bus control register
DRCRA
DRCRB
RTMCSR
RTCNT
RTCOR
Figure 6.1 Block Diagram of Bus Controller
Rev.5.00 Sep. 12, 2007 Page 109 of 764
REJ09B0396-0500